Phase locked loop (PLL) frequency synthesizers are often used in radiotelephone transmitters to generate a desired frequency for modulating a data signal. The PLL frequency synthesizer having a single phase detector and a single charge pump requires a compromise between fast lock time and good spectral purity. A fast locking control loop often loses lock easily due to outside perturbations. Although the control loop rapidly re-acquires lock, it is inherently unstable, therefore, it does not provide sufficient spectral purity for most applications. Conversely, a slow locking control loop requires a long length of time to acquire frequency lock. In a radiotelephone system such as a TDMA (time division multiple access) radiotelephone system, the PLL frequency synthesizer is required to turn on and turn off. A slow locking loop is insufficient to provide the speed required for the control loop.
In the past, PLL frequency synthesizers have utilized two independent control loops, a wide bandwidth loop to provide the required rapid acquisition lock during initial start up and after the loss of frequency lock and a narrow bandwidth loop for providing stability after the PLL frequency synthesizer has attained lock. One such embodiment which has been developed is illustrated in FIG. 1. Here, the PLL frequency synthesizer utilizes two phase detectors 101, 103 and two charge pumps 105, 107. The phase detector with the deadzone circuit 103, the high current charge pump 107 and the wide band filter 110 together provide a fast locking loop at initial start-up and when re-acquiring lock for the PLL frequency synthesizer. Phase detector without deadzone 101, the low current charge pump 105 and the narrow band filter 111 together are used to provide a stable control loop after the PLL frequency synthesizer has maintained lock. One example of combining the narrow band filter 111 and the wide band filter 110, implemented in the past, is shown in FIG. 2. This loop filter 209 provides a traditional second order loop characteristic for each of the two loops. The loop characteristics can be set independently.
It would be advantageous to provide a PLL frequency synthesizer which provides higher order loop characteristics for both the wide bandwidth and narrow bandwidth control loops. Additionally, it would be advantageous to provide a PLL frequency synthesizer which utilizes fewer parts for implementing.